1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof. More particularly, this application relates to a semiconductor device having a capacitor and a fabrication method thereof.
2. Description of the Related Art
Generally, semiconductor memory devices, in particular, dynamic random access memory (DRAM) devices, have capacitors for storing data in unit cells. More particularly, a unit cell of a DRAM device consists of a cell capacitor and an access transistor which is directly connected to the cell capacitor.
However, corresponding to the continuous increase of the semiconductor device's integration density, the unit cell area has been decreased dramatically. As a result of the decreased capacitor size, the capacitance of the unit cell capacitor becomes smaller. This results in a decrease of the capability for storing a data in a unit cell. Specifically, sometimes the unit cell may lose the data which was stored in the cell, and the memory device may make functional errors. Therefore, capacitance of a unit cell capacitor must be maintained in order to maintain proper device function in a high density device.
It is well known to increase surface area of a unit cell capacitor's storage node to increase capacitance of the unit cell capacitor. For example, in the case of a stacked storage node or a cylindrical storage node, the capacitance of the unit cell can be increased by increasing the height of the unit cell capacitor.
However, increasing the height of the storage node can result in several problems. For example, as the height of the storage node is increased, it may be very difficult to pattern conductive layers as storage nodes. Also, electrical bridges between adjacent storage nodes will be increased significantly due to leaning phenomena of the storage nodes.
A cylindrical capacitor storage node and a fabrication method are described in U.S. Pat. No. 6,329,683 by Kohyama et al., entitled “Semiconductor Memory Device and Manufacturing Method Thereof Which Make it Possible to Improve Reliability of Cell-Capacitor and Also to Simplify the Manufacturing Processes.”
Kohyama et al. described a semiconductor memory device having a cylinder type storage node and a manufacturing method thereof. In Kohyama, et al., an isolation region defining active regions is formed on a semiconductor substrate. Each of the active regions has a major axis and a minor axis, and the active regions are separated by a given distance. An insulating layer is formed on the semiconductor substrate. Contact plugs which are connected to the active regions are formed in the insulating layer. Cylinder type storage nodes having an elliptical shape and protruding from the contact plugs are formed on the contact plugs.
Major axes of the above elliptical cylinder storage nodes are parallel to the major axes of the active regions. However, because of the increase of the devices' density, the space between the minor axes of the capacitor storage nodes may be narrower. As a result, the possibility of a bridge being formed between the storage nodes increases. Therefore, recently, a circle type storage node instead of the elliptical type storage node has been suggested.
Unfortunately, the circle type storage node has less capacitance than the elliptical type storage node because total surface area of the circle type storage node is lower than that of the elliptical type storage node.
Therefore, now, in order to increase the surface area of the capacitor storage node and to prevent the electrical bridge, the storage nodes may be formed having a portion which is not connected to the contact plugs at their bottom surface. As a result, a buffer conductive layer is formed on the contact plug to increase the contact area between the storage nodes and the contact plugs.
FIGS. 1A through 1E are cross-sectional views illustrating a conventional method of fabricating a semiconductor device having a cylindrical storage node.
Referring to FIG. 1A, an insulating layer 105 is formed on a semiconductor substrate 100. A contact hole 110 is formed in the insulating layer to expose a portion of the semiconductor substrate by patterning the insulating layer. A conductive layer made of polysilicon is formed on the insulating layer and in the contact hole. A contact plug 115a is formed in the insulating layer, and a buffer conductive pattern 115b is formed on the insulating layer 105 and the contact plug 115a by patterning the conductive layer. The buffer conductive pattern 115b prevents a bad contact profile between the contact plug 115a and a storage node which will be formed on the contact plug 115a. 
Referring to FIG. 1B, an etching stopping layer 125 made of silicon nitride is formed on the insulating layer 105 and the buffer conductive layer 115b. A first mold layer 130 and a second mold layer 135 are formed on the etching stopping layer 125. The first mold layer 130 should have a different and higher etching rate compared with the second mold layer 135. For example, if the first mold layer 130 is a BPSG (Boron Phosphorous Silicate Glass) layer, the second mold layer 135 may be a PE-TEOS (Plasma Enhanced-Tetraethylortho Silicate) layer.
A storage node contact hole 140 is formed to expose the buffer conductive layer 115b by patterning the first and second mold layers 130, 135 and the etching stopping layer 125. A portion of the bottom area of the storage node contact hole 140 is not formed on the buffer conductive layer 115b such that the buffer conductive layer 115b is at least partially exposed.
Referring to FIG. 1C, the semiconductor substrate having the storage node contact hole 140 is cleaned with a cleaning chemical solution. A natural oxide layer and any defects which are formed on the surface of the buffer conductive layer are removed by the cleaning process. Generally, the cleaning chemical solution comprises Hydrogen Fluoride (HF). Thus, the first and second mold layers 130, 135 are also etched isotropically by the cleaning chemical solution. The first mold layer 130 is etched more than the second mold layer 135 because the first mold layer 130 has a higher etching rate in the HF chemical solution than the second mold layer 135. Accordingly, an enlarged storage node contact hole 140a is formed in the first mold layer 130. The enlarged storage node contact hole 140a is relatively close to the etching stopping layer 125 formed on an adjacent buffer conductive layer 140 as illustrated in the circle W1 of FIG. 1 C. The proximity of the storage node contact hole 140a is affected by the duration of the cleaning process. Generally, the longer the cleaning process is performed, the greater amount the first mold layer 130 is etched, and, therefore, the smaller the gap between the etching stopping layer 125 formed on the adjacent buffer conductive layer 115b and a storage node layer which will be formed the conductive layer will be.
A storage node layer 145 is formed on the second mold layer 135 and the storage node contact. The storage node layer 145 generally consists of a polysilicon layer having a good deposition characteristic. A passivation layer 150 is formed on the storage node layer 145 to fill in the storage node contact. The passivation layer 150 is an oxide layer, a BPSG (Boron Phosphorus Silicate Glass) layer, or a PSG (Phosphorous Silicate Glass).
Referring to FIG. 1D, a planarizing process is performed to form storage nodes 145a which are separated from each other by polishing or etching the passivation layer 150 until the second mold layer 135 is exposed.
Referring to FIG. 1E, the first and second mold layers 130, 135 and the passivation layer 150 are removed to expose the inner and outer sidewall of the storage nodes 145a. A dielectric layer 155 is formed on the surface of the storage nodes 145a. As shown in the circle W2 of FIG. 1E, the dielectric layer 155 formed on the storage nodes can be connected to the adjacent dielectric layer formed on adjacent buffer conductive layer 115b. 
It is also possible for the storage nodes 145a to be connected to the etching stopping layer 125 when the first and second mold layers 130, 135 and the passivation layer 150 are removed if the storage nodes 145a lean to the etching stopping layer 125 formed on the adjacent buffer conductive layer 115b. Hence, in this case, the capacitance of each storage node will be reduced because the total surface area of each storage node 145a is reduced. The thickness of the storage nodes 145a may be reduced to prevent the dielectric layer 155 formed on the storage nodes 145a from connecting to the adjacent dielectric layer 155 formed on the adjacent buffer conductive layer 115b. Unfortunately, in this case, the storage nodes can easily lean by a large amount. Because of these and other problems, improved storage node structures and methods of forming the same are required.